1. Field of the Invention
The present invention relates to an ATM (Asynchronous Transfer Mode) communication control device for performing the processing of a subordinate (lower layer) portion of an ATM protocol between a terminal and an ATM network, and an ATM controller which shares the processing in the device.
2. Description of Related Art
In an ATM network, communication is performed according to an ATM protocol between an ATM communication control device and plural terminals which are connected to the ATM communication control device through lines. The ATM communication control device serves to share various kinds of processing of a subordinate (lower layer) portion of the ATM protocol to divide a variable-length packet generated at a terminal into fixed-length cells and then transmit the fixed-length cells to a line, and also serves to generate a packet on the basis of cells received through a line and deliver the packet thus generated to a terminal. The ATM protocol is being standardized by an ATM forum on the basis of the recommendation of the ITU (International Telecommunication Union).
There has been hitherto proposed an ATM controller which realizes, by an LSI, ATM layer processing for performing cell transmitting and receiving control and AAL (ATM Adaptational Layer) processing for performing cell segmentation and reassembly (both kinds of processing are hereinafter referred to as "ATM protocol processing") of the processing of the ATM communication control device. For example, in ".mu.PD98401" described in NEC Technical Report (Vol. 47, NO. 7/1994), the ATM protocol processing is achieved by a wired logic whose processing procedure is fixed. According to this technique, the processing speed can be increased, however, the processing content cannot be altered. The ATM protocol contains some kinds of processing which have not yet been standardized, for example, processing for cells of a management system such as OAM (Operation Administration and Maintenance) cells, RM (Resource Management) cells used to protect the network and the end system from congesting, etc. Therefore, the ATM controller is preferably designed to support the alteration of these non-standardized processing.
"ATMizer" as described in Nikkei Electronics (Apr. 11, 1994, No. 605, pp.17-18) is known as an ATM controller which is designed to support the alteration of the processing. This controller contains a microprocessor therein, and it achieves most of the ATM protocol processing containing an analysis work of a cell header, a cell segmentation/reassembly work, etc. by software processing. However, since the software processing needs a lot of overheads, this controller is equipped with a microprocessor having high performance and large scale, and the microprocessor is operated at high speed.
As described above, since the conventional ATM controller needs a microprocessor having high performance and large scale, a fine process technology is required in a manufacturing process, and thus the manufacturing cost thereof is high. Further, since the microprocessor must be operated at high speed, power consumption is also increased.
Nevertheless, at the setting time of a virtual connection (VC) which can be uniquely identified by VPI (Virtual Path identifier)/VCI (Virtual Channel Identifier) In the ATM, QS (Quality of Service) indicating, for example, how degree the cell delay variation is permitted (i.e., the maximum level of the permitted cell delay variation) In accordance with the type of traffic to be transferred on the virtual connection, and a cell rate can be required to the network and the end system. Actually, a category (class) to be used at the setting time of the VC is selected from four ATM service categories (CBR (Constant Bit Rate): fixed rate service, VBR (Variable Bit Rate): variable rate service, ABR (Available Bit Rate): service for varying the rate in accordance with the congestion of the network, UBR (Unspecified Bit Rate): unspecified and non-guaranteed service) which are defined as functions of the ATM layer, and a cell rate (transmission rate) is requested.
The ATM controller which is necessary to connect to ATM-LAN is required to individually transmit each cell every VC in accordance with a service category declared at the VC setting (signaling) time and at a transmission rate declared at the VC setting time.
The following two methods are known to perform a traffic shaping function which is supported by the existing ATM controller. According to one method, four rate queues are prepared in conformity to two priorities in a hardware, a peak rate is specified in conformity to the rate queue and plural VCs registered in the rate queue are accessed at the specified rate by a round robin system to transmit cells. According to another method, a table in which the order of VCs to transmit the cells is registered is prepared in advance on the basis of the cell rate of the whole VCs, and the table is accessed every fixed period in a hardware to transmit the cell corresponding to the registered VC.
An SARA chip produced by TransSwitch company is known as an ATM controller having the former traffic shaping function, and an ATM SAR chip (IDT77201) produced by Integrated Device Technology company is known as an ATM controller having the latter traffic shaping function.
However, in such a conventional device, in order to perform the transmit traffic control corresponding to a service category and a cell rate which are declared in conformity to a VC and also defined in the ATM protocol, it is needed to consider the cell rate In conformity to the VC by a driver of the ATM controller, and also it is needed to reconsider the schedule of the whole cell rate when a VC is set.
For example, as well known in the prior arts as described above, a table is required to be beforehand prepared for allotment of a peak rate to a rate queue and a schedule.
In general, in a network card for connection to ATM-LAN, the design is made so that no local processor for the driver of the ATM controller is mounted, so that in order to reduce the cost the traffic management corresponding to the VC must be performed in a CPU at the terminal side.